Abr Architecture and Simulation for an Input-buffered and Per-vc Queued Atm Switch

This paper proposes an innovative concept, called virtual output queue, to support available bit rate (ABR) traffic on an input-buffered, per virtual circuit (VC) queued switch. This technique allows ABR models developed for output-buffered systems to be migrated to an inputbuffered system. In order to evaluate the virtual output queue and to compare different ABR algorithms, a simulator of the ATM testbed at the University of Illinois has been enhanced with ABR functions. This paper provides simulation results for the input-buffered variation of the ERICA+ algorithm. INTRODUCTION ABR is designed for computer data transmission in ATM networks. For an ABR connection, the source receives feedback from the network and adjusts its rate according to this information. The feedback information is carried within special cells, called Resource Management cells (RM cells). RM cells are periodically inserted into the stream of ABR data cells. As a consequence of the feedback mechanism, cell loss is minimized and the available bandwidth is shared fairly by the ABR connections. The first section of this paper presents the virtual output queue, a technique which approximates the length of an output-buffered queue for ABR traffic on an inputbuffered switch. The next section deals with the general implementation of ABR fair-share rate algorithms with the virtual output queue. The last section shows simulation results for ERICA+ with current cell rate (CCR) measurement. More simulations have been presented in [1] and [2], where the DMRCA algorithm [3] and ERICA+ [4] have been adapted to an inputbuffered switch architecture. Input-Queuing The iPOINT switch [5], [6] developed at the University of Illinois features an input-buffered architecture. The main advantage of this design is its high scalability. For an input-buffered switch, the memory bandwidth is independent of the number of ports. At most, only one cell may be written into the memory and only one cell may be read from the memory per cell slot [7]. Through the use of a cell scheduler, the switch fabric needs only to provide crossbar functionality [8]. The major shortcoming of an input-queued switch architecture is the head-of-line (HOL) blocking problem, that occurs when simple FIFO queues are used. For the iPOINT switch, the iiQueue has been developed, featuring a three-dimensional queue (3DQ). The 3DQ sorts the cells according to three criteria: their connection, their priority, and their output port [9]. This provides near-100% link utilization and supports QoS for multiple traffic types. THE VIRTUAL ABR OUTPUT QUEUE CONCEPT This paper presents a concept that allows ABR algorithms, designed for an output-buffered switch to be used in an input-buffered and per-VC queued switch. This technique uses in-band communication to transmit data among the different modules of the switch. The supplementary information is carried in unused bytes of the RM cell and therefore does not affect the throughput of the switch. The computational complexity of the virtual output queue is independent of the number of VCs. The Problem of Input Queuing ABR algorithms need to measure the congestion of an outgoing link. Two schemes are possible: measurement of the link utilization and/or measurement of the ABR queue length. The most powerful algorithms use queue length measurement. It is not simple to characterize the outgoing ABR queue length on an input-buffered switch with per-VC queuing. Consider the simple network in Figure 1, featuring one switch, three sources, and one destination. Traffic is flowing from the three ABR sources (S1, S2, and S3) to the corresponding destination (D). Three ports of the switch are connected to the three sources (S1, S2, and S3). The fourth port of the switch is connected to the destination (D). When the sources are not internally bottlenecked, each is able to transmit at the maximum speed of the link. In this case, the link connected to the destination becomes congested. For an input-buffered switch, this bottlenecked link triggers queue growth at each input port with incoming traffic.